16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation

Author

Boeuf, F. ; Skotnicki, T. ; Monfray, S. ; Julien, C. ; Dutartre, D. ; Martins, J. ; Mazoyer, P. ; Palla, R. ; Tavel, B. ; Ribot, P. ; Sondergard, E. ; Sanquer, A.

Author_Institution

STMicroelectronics, Grenoble, France

fYear

2001

fDate

2-5 Dec. 2001

Abstract

In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m and I/sub off/=0.8 /spl mu/A//spl mu/m and demonstrate that the FET principle is still confirmed at room temperature. We have deliberately used a non-overlapped SD/gate architecture, showing that, with adapted channel doping, it not only performs equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable. Finally, we show that quantization of energy in the channel motivates a study of performance at low temperature, and that the leading effect at low temperature and low voltage is Coulomb blockade.

Keywords

Coulomb blockade; MOSFET; cryogenic electronics; nanotechnology; semiconductor device manufacture; 16 nm; 16 nm planar NMOSFET manufacture; 35 mK to 300 K; Coulomb blockade; Si/sub 0.75/Ge/sub 0.25/-Si-SiO/sub 2/; adapted channel doping; energy quantization; low temperature; mesoscopic effects; nanometer MOSFET; nonoverlapped SD/gate architecture; quantum effects; room temperature; selective SiGe etching; small channel size; state-of-the-art CMOS process; CMOS process; Design optimization; Doping; FETs; Lithography; MOS devices; MOSFET circuits; Manufacturing processes; Nanoscale devices; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979589

Filename

979589