The IC design of a high speed RSA processor

Author

Yang, Ching-Chao ; Jen, Chein-Wei ; Chang, Tian-Sheuan

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1996

fDate

18-21 Nov 1996

Firstpage

33

Lastpage

36

Abstract

In this paper, we proposed a new algorithm based on Montgomery´s algorithm to calculate modular multiplication that is the core arithmetic operation in RSA cryptosystem. Since the critical path delay in modular multiplication operation is reduced, the new design yields a very fast implementation. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6 μm SPDM cell library. By our modified modular exponentiation algorithm, it takes about 1.5 n² clock cycles to finish one n-bit RSA modular exponentiation operation in our architecture. The simulation results show that we can operate up to 125 Mhz, therefore the baud rate of our 512-bit RSA processor is about 164 k bits/sec

Keywords

digital arithmetic; integrated circuit design; public key cryptography; 0.6 micron; 125 MHz; 164 kbit/s; 512 bit; Compass SPDM cell; IC design; Montgomery algorithm; arithmetic operation; critical path delay; cryptosystem; high speed RSA processor; modular exponentiation; modular multiplication; Arithmetic; Authentication; Clocks; Delay; Hardware; High speed integrated circuits; Libraries; Pipelines; Public key cryptography; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-3702-6

Type

conf

DOI

10.1109/APCAS.1996.569212

Filename

569212