Statistical modeling of reliability and scaling projections for flash memories

Author

Ielmini, D. ; Spinelli, A.S. ; Lacaita, A.L. ; Modelli, A.

Author_Institution

Dipt. di Elettronica e Informazione, Politecnico di Milano, Milan, Italy

fYear

2001

fDate

2-5 Dec. 2001

Abstract

A new physically-based model for reliability analysis of flash memories is presented. The model provides a quantitative description of the distribution of the stress-induced leakage current (SILC) in large memory arrays, considering the statistics of the defects responsible for the trap-assisted tunneling (TAT) current. Simulation results are in good agreement with SILC statistics over oxide thicknesses of 6.5, 8.8 and 9.7 nm. The model can be used to quantitatively evaluate the failure rate under different conditions and assess the trade-off between oxide thinning and device reliability. The relationship between tunnel oxide scalability and defect concentration is also quantitatively assessed.

Keywords

failure analysis; flash memories; integrated circuit modelling; integrated circuit reliability; leakage currents; tunnelling; 6.5 nm; 8.8 nm; 9.7 nm; NOR-type flash arrays; SILC statistics; defect concentration; defect statistics; failure rate; flash memories; large memory arrays; oxide thicknesses; oxide thinning; physically-based model; reliability analysis; scaling projections; simulation results; statistical modeling; stress-induced leakage current; trap-assisted tunneling current; tunnel oxide scalability; Current density; Current measurement; Density measurement; Displays; Electrons; Leakage current; Probability distribution; Threshold voltage; Tunneling; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979608

Filename

979608