Abstract :
In scaling down the dimensions of the transistors in integrated circuits, major issues need to be solved. As we approach the resolution limit of the lithographic tool, extensive modifications of the patterns need to be performed on the mask in order to match the expected features on the circuit. More and more trade-offs need to be addressed in designing complex circuits like power consumption, variability, error rate, etc.: a better interplay between the technology constraints and the design complexity has to be developed. Moving to non conventional CMOS (e.g. FinFET) induces specific issues to be dealt with through the design style. On the far end of this spectrum emerging research devices and architectures, as they are called in the ITRS roadmap, may need ‘out-of-the box’ thinking in the way complex systems and applications will be integrated.
