DocumentCode
2168436
Title
FSimGP^2: An Efficient Fault Simulator with GPGPU
Author
Li, Min ; Hsiao, Michael S.
Author_Institution
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
fYear
2010
fDate
1-4 Dec. 2010
Firstpage
15
Lastpage
20
Abstract
General Purpose computing on Graphical Processing Units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. But GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, FSimGP2, that exploits the high degree of parallelism supported by a state-of-the-art graphic processing unit (GPU) with the NVIDIA Compute Unified Device Architecture (CUDA). A novel three-dimensional parallel fault simulation technique is proposed to achieve extremely high computation efficiency on the GPU. The experimental results demonstrate a speedup of up to 42× compared to another GPU-based fault simulator and up to 53× over a state-of-the-art algorithm on conventional processor architectures.
Keywords
computer graphic equipment; fault simulation; general purpose computers; microprocessor chips; software engineering; 3D parallel fault simulator; FSimGP2; algorithmic design; general purpose computing; graphical processing units; software development; Circuit faults; Computational modeling; Graphics processing unit; Instruction sets; Integrated circuit modeling; Logic gates; Parallel processing; Fault simulation; compute unified device architecture (CUDA); general purpose computation on graphics processing unit (GPGPU); parallel algorithm; single instruction multiple threads (SIMT);
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ATS), 2010 19th IEEE Asian
Conference_Location
Shanghai
ISSN
1081-7735
Print_ISBN
978-1-4244-8841-4
Type
conf
DOI
10.1109/ATS.2010.12
Filename
5692213
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