Title :
Optimum SNS to binary conversion algorithm and FPGA realization
Author :
Pace, P.E. ; Styer, D. ; Ringer, W.P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA
fDate :
31 May-3 Jun 1998
Abstract :
Folding analog-to-digital converters, fold the input signal symmetrically in order to reduce the number of comparators required to amplitude analyze the signal (preprocessing). The optimum symmetrical number system (OSNS) formulation is a direct consequence of the need to extract the maximum amount of information from a symmetrically folded waveform. OSNS folding converters require the minimum number of comparator circuits for any desired resolution. Although there is a direct correspondence between the OSNS and the residue number system, the symmetrical residues cannot be converted to a binary value (e.g., using the Chinese Reminder Theorem) in a straightforward manner. This paper presents an efficient algorithm that converts the symmetrical residues within a three moduli (2k+1,2k,2k -1) OSNS to the equivalent binary representation. Also presented is a pipelined field programmable gate array (FPGA) realization of the algorithm
Keywords :
analogue-digital conversion; field programmable gate arrays; residue number systems; OSNS folding converters; analog-to-digital converters; comparator circuits; equivalent binary representation; field programmable gate array; folding ADC; optimum SNS to binary conversion algorithm; optimum symmetrical number system; pipelined FPGA realization; symmetrical residues conversion; symmetrically folded waveform; Analog-digital conversion; Circuits; Data mining; Data preprocessing; Dynamic range; Equations; Field programmable analog arrays; Field programmable gate arrays; Signal analysis; Signal resolution;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706882