A 3-D BiCMOS technology using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)

In this paper, a novel 3-D BiCMOS technology is proposed and demonstrated for the first time. To implement the 3-D BiCMOS structure, NMOS transistors are fabricated on the bulk substrate (bottom layer), PMOS transistors are fabricated on the single crystal top layer which is obtained using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE), and BJTs are fabricated in the SEG regions. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than those fabricated on SOI wafers, and the BJTs also have high performance with a peak f/sub T/ of 17 GHz and a peak f/sub max/ of 14 GHz. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuits applications.