Title :
Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits
Author :
Kole, Dipak K. ; Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Author_Institution :
Inf. Technol. Dept., Bengal Eng. & Sci. Univ., Shibpur, India
Abstract :
Logic synthesis of reversible circuits has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. This article presents an efficient algorithm to derive an optimal test set (OTS) for detection of multiple missing-gate faults in a reversible circuit implemented with k-CNOT gates. It is shown that the OTS is sufficient to detect all single missing-gate faults (SMGFs) and all detectable repeated gate faults (RGFs). Experimental results on some benchmark circuits are also reported.
Keywords :
CMOS logic circuits; fault diagnosis; logic testing; quantum gates; CMOS circuits; logic synthesis; multiple missing-gate fault detection; optimal test set; partial missing-gate fault; quantum computation; quantum k-CNOT gates; repeated-gate fault; reversible circuits; single missing-gate fault; stuck-at fault; Arrays; Circuit faults; Integrated circuit modeling; Logic gates; Quantum computing; Semiconductor device modeling; Testing; Missing-gate faults; quantum computing; reversible logic; testable design; universal test set;
Conference_Titel :
Test Symposium (ATS), 2010 19th IEEE Asian
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-8841-4
DOI :
10.1109/ATS.2010.15