DocumentCode
2168561
Title
Testing of very large systems: a hierarchical approach to fault coverage evaluation
Author
Distante, F. ; Sami, M.G. ; Sciuto, D.
Author_Institution
Dipartimento di Elettronica, Politecnico di Milano, Italy
fYear
1991
fDate
29-31 Jan 1991
Firstpage
292
Lastpage
298
Abstract
The authors consider general, uncommitted systems whose only particular characteristic is that of affording a hierarchical, structured organization. For such systems, they propose a graph-based representation of the testing problem. First, it is seen how such representation makes it possible to define the relationship between test vectors and faults at one abstraction level: then, a multiple-level extension is introduced. This multiple-level representation is used to evaluate the limits of test coverage that can be achieved when higher levels of abstraction are used and to introduce the definition of test procedures at a high abstraction level
Keywords
VLSI; digital integrated circuits; integrated circuit testing; abstraction level; fault coverage evaluation; graph-based representation; hierarchical approach; limits of test coverage; multiple-level extension; multiple-level representation; structured organization; test vectors; testing problem; uncommitted systems; Acceleration; Circuit faults; Circuit simulation; Circuit testing; Context modeling; Digital systems; Phased arrays; Proposals; System testing; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9126-3
Type
conf
DOI
10.1109/ICWSI.1991.151729
Filename
151729
Link To Document