A Localized Power Control mixing hopping and Super Cut-Off techniques within a GALS NoC

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. We propose in this paper a complete dynamic voltage and frequency scaling architecture for IP units within a GALS NOC. network-on-chip architecture combined with a globally asynchronous locally synchronous paradigm is a natural enabler for DVFS mechanisms. GALS NoC provides scalable communications and a natural split between timing domains. The proposed low power architecture is based on the association of a local clock generator and a local power control mixing VDD-hopping and super cut-off techniques. No fine control software is required during voltage and frequency scaling. A minimal latency cost is observed together with an efficient local power control.