Title :
Tunnel Transistors for Low Power Logic
Author :
Datta, Soupayan ; Bijesh, R. ; Liu, Hongying ; Mohata, D. ; Narayanan, Vijaykrishnan
Author_Institution :
Dept. of Electr. Eng., Pennsylvania State Univ., Univeristy Park, PA, USA
Abstract :
Tunnel transistor (TFET) as steep slope device to enable supply voltage scaling is explored at the device level as well as circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry outperform Si FINFET at Vcc <; 0.3V. Design considerations of TFET based circuits for logic applications are investigated and performance benchmarked with Si FinFET technology.
Keywords :
MOSFET; elemental semiconductors; logic devices; low-power electronics; silicon; tunnel transistors; Si; Si FinFET technology; circuit level; heterojunction TFET; low power logic; steep slope device; supply voltage scaling; tunnel transistors; Adders; FinFETs; Gallium arsenide; Integrated circuit modeling; Logic gates; Silicon; Tunneling;
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/CSICS.2013.6659248
