SRAM memory cell leakage reduction design techniques in 65nm low power PD-SOI CMOS

The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques change the strength of individual cell transistor, thus modifying the cell stability during the first read access following a long period of idle mode. The conclusions of the paper show that letting the bit lines float during the idle mode is mandatory to diminish the cell leakage current and help to protect the cell content against the bit-line aggressions.