Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Author

Collaert, N. ; von Arnim, K. ; Rooyackers, R. ; Vandeweyer, T. ; Mercha, A. ; Parvais, B. ; Witters, L. ; Nackaerts, A. ; Sanchez, E. Altamirano ; Demand, M. ; Hikavyy, A. ; Demuynck, S. ; Devriendt, K. ; Bauer, F. ; Ferain, I. ; Veloso, A. ; Meyer, K. De

Author_Institution

IMEC, Leuven

fYear

2008

fDate

2-4 June 2008

Firstpage

59

Lastpage

62

Abstract

While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.

Keywords

MOSFET circuits; SRAM chips; digital integrated circuits; integrated circuit design; large scale integration; FinFET; HfSiON-TiN; SRAM cell; large-scale integration; size 10 nm; size 30 nm; size 32 nm; voltage 0.6 V; voltage 10 mV; Dielectrics; FinFETs; Image motion analysis; Implants; Large scale integration; Optical devices; Random access memory; Ring oscillators; Scalability; Tin; SOI FinFET; SRAM; ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567246

Filename

4567246