A fast router and placement algorithm for wafer scale integration and wafer scale hybrid packaging

Author

McDonald, J.F. ; Donlan, B.J. ; Russinovich, M.E. ; Philhower, R. ; Nah, K.S. ; Greub, H.

Author_Institution

Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA

fYear

1991

fDate

29-31 Jan 1991

Firstpage

331

Lastpage

340

Abstract

The authors describe an algorithm developed for discretionary wafer routing needed for wafer scale integration (WSI) or multichip packaging. A very fast multilayer line probe router has been developed and implemented. The router uses a collection of depth-first heuristics to provide an extremely fast route with exceptional wiring quality and very high completion rate. The search algorithms and data structures are significantly different from those of D. Hightower (1969). These differences make it possible to route the special kinds of wiring needed for WSI in under a minute of VAX 6410 CPU time in many cases. Such a high-speed router will be necessary when line routing is to proceed at wafer throughput rates for fabrication

Keywords

VLSI; circuit layout CAD; hybrid integrated circuits; VAX 6410; depth-first heuristics; discretionary wafer routing; fast router and placement algorithm; high completion rate; high-speed router; multichip packaging; multilayer line probe router; wafer scale hybrid packaging; wafer scale integration; Digital systems; Electronics packaging; Fabrication; Integrated circuit interconnections; Power system interconnection; Printed circuits; Probes; Routing; Wafer scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-9126-3

Type

conf

DOI

10.1109/ICWSI.1991.151730

Filename

151730