• DocumentCode
    2168905
  • Title

    Experimental and numerical reliability investigations of FCOB assemblies with process-induced defects

  • Author

    Schubert, A. ; Dudek, R. ; Kloeser, J. ; Michel, B. ; Reichl, H. ; Hauck, T. ; Kaskoun, K.

  • Author_Institution
    Fraunhofer Inst. for Reliability & Microintegration, Berlin, Germany
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    624
  • Lastpage
    632
  • Abstract
    To develop comprehensive design guidelines, models and experiments cannot overlook process-induced imperfections in the flip chip on board (FCOB) assemblies. The following items were noted as being significant factors which were used for modeling and by thermal cycling tests: (a) varying standoff-heights and alternative bump sizes, (b) underfill-particle settling, (c) underfill-void effects, (d) underfill-to-bump coverage, (e) asymmetrical fillets vs. symmetrical fillets. A detailed numerical and experimental reliability study of perfect and imperfect flip chip assemblies has been completed. Experimental studies of the failure modes and of the mean cycles to failure are in good agreement with the failure modes and life time, as predicted by FEM for the different technological variants. A hierarchy of influences was worked out in three levels (important, medium, negligible). Most important imperfections resulting in a strong reliability decrease are particle settling, asymmetrical fillets and small and big voids
  • Keywords
    chip-on-board packaging; finite element analysis; flip-chip devices; integrated circuit modelling; integrated circuit reliability; voids (solid); FCOB assemblies; Si; asymmetrical fillets; experimental reliability; failure modes; finite element analysis; flip chip on board assemblies; mean cycles to failure; numerical reliability; particle settling; process-induced defects; reliability; symmetrical fillets; thermal cycling tests; underfill-particle settling; underfill-to-bump coverage; underfill-void effects; voids; Assembly; Delamination; Finite element methods; Flip chip; Geometry; Numerical simulation; Semiconductor device reliability; Silicon; Solid modeling; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th
  • Conference_Location
    Las Vegas, NV
  • Print_ISBN
    0-7803-5908-9
  • Type

    conf

  • DOI
    10.1109/ECTC.2000.853224
  • Filename
    853224