Author_Institution :
Nat. Inst. of Stand. & Technol., Boulder, CO, USA
Abstract :
At issue was the thermomechanical response of microvias in a high-density interconnect (HDI) substrate. The HDI package containing microvias, blind vias, solder bumps, and line traces was thermally cycled five times between -55 and 125°C in a scanning electron microscope. The electron-beam moire technique was used to measure displacements in the package at the temperature extremes and to measure permanent deformations due to the effect of the mismatch in the coefficient of thermal expansion (CTE) of the contained materials. Further thermal cycling was conducted over the same temperature range in an environmental chamber, for a total of 34 thermal cycles. The microvias experienced minimal permanent deformation (~0.2% compression) after 5 cycles, and no visual deformation in the way of cracks or plasticity during cycling in the environmental chamber. Other areas of the package, however, experienced cracking due to the mismatch in CTE of adjacent materials, and deformation and cracks due to thermal fatigue. Cracks due to CTE mismatch occurred between the polyimide layer and the Si chip. These cracks propagated to and around the solder bumps, between the solder and the polyimide, underfill, and solder mask. Interfacial cracks due to CTE mismatch also appeared between the printed circuit board and the wall of the blind via. Evidence from the moire fringes indicates that these cracks initiated in the first excursion to -55°C. After 34 thermal cycles the moire fringes in the solder bumps were convoluted, showing extensive plastic flow. Images from the bases of the solder bumps show classic fatigue crack initiation and growth behavior-void nucleation and coalescence. Failure of the solder bumps, providing stress relief, made continuation of the test to induce deformation in the microvias moot
Keywords :
chip scale packaging; flip-chip devices; integrated circuit interconnections; integrated circuit testing; moire fringes; plasticity; substrates; thermal expansion; thermal stress cracking; -55 to 125 C; -55 to 125°C; HDI package; Si; Si chip; blind vias; coalescence; coefficient of thermal expansion; cracks; deformations; displacements; electron-beam moire technique; flip-chip HDI substrate; high-density interconnect substrate; interfacial cracks; line traces; microvias; mismatch; permanent deformation; plastic flow; plasticity; polyimide layer; scanning electron microscope; solder bumps; solder mask; thermal cycling; thermal fatigue; thermally induced deformations; thermomechanical response; visual deformation; void nucleation; Displacement measurement; Fatigue; Integrated circuit interconnections; Packaging; Polyimides; Scanning electron microscopy; Temperature; Thermal conductivity; Thermal expansion; Thermomechanical processes;