Parallel LFSR Reseeding with Selection Register for Mixed-Mode BIST

This paper presents a new parallel LFSR reseeding with selection register for mixed-mode BIST in order to reduce the number of test data. The dynamic seeds were injected in parallel form through the LFSR, phase shifter, and scan chains, respectively. The selection register was added to improve the efficiency of encoding test data. For seed computing, after the equations were formed, they were solved by Gauss-Jordan elimination. The experimental results for ISCAS 89 benchmark circuits indicate the significant improvement in terms of test data. There are several main advantages of proposed approach such as 100% test coverage, low test data, low test application time, high fault coverage as intended by the deterministic patterns, etc.