Low-Complexity Two Instructions Set Computer for Suffix Sort in Burrow Wheeler Transform

The Burrow Wheelers Transform (also called the block sorting compression) was referred to as the jewel loss less compression due its effectiveness and is used as the core algorithm in bzip2 compressor. With much attention given, hardware realization of the BWT algorithm has been limited due to the complexity of suffix sorting computation. Given the small hardware-footprint design trend, we propose the use of a reconfigurable FPGA platform and unified computer architecture with minimal hardware components. In this paper, we are presenting a low-complexity two instructions set computer architecture (TISC) for the lexicographical sorting in Burrow Wheelers Transform. The proposed architecture has been implemented and tested using the DK Design Suite software environment, which provides a Handel-C Hardware Descriptive language to ease the design process. A Celoxica RC10 board which houses the Spartan 3 XCS1500L-4 FPGA is used.