A low power 12-bit and 30-MS/s pipeline analog to digital converter in 0.35μm CMOS

The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash. A CMOS 0.35 mum process is used, and the dynamic range covered is 2 V. The analog part of the converter can be quickly (a couple of mus) switched to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converterpsilas layout including the digital correction stage is only 1.7 mm*0.6 mm, and the total dc power dissipation is 35 mW.