Title :
SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures
Author :
Nishida, Y. ; Sayama, H. ; Ohta, K. ; Oda, H. ; Katayama, M. ; Inoue, Y. ; Morimoto, H. ; Inuishi, A.
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A novel device architecture is presented, where surface channel (SC) pMOSFETs and buried channel (BC) pMOSFETs are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by the BC structure for I/O and analog circuits, and high-speed and high integration are realized by the SC structure for core circuits in System-on-a-Chip (SoC).
Keywords :
CMOS analogue integrated circuits; MOSFET; high-speed integrated circuits; hot carriers; integrated circuit noise; integrated circuit reliability; 1.2 V; 3.3 V; I/O circuits; SoC CMOS technology; analog circuits; buried channel pMOSFET; high-performance core circuits; high-speed high integration; hot carrier injection; low noise characteristics; negative bias temperature instability; reliability; surface channel pMOSFET; system-on-chip; Analog circuits; CMOS analog integrated circuits; CMOS technology; Human computer interaction; Integrated circuit reliability; MOSFETs; Negative bias temperature instability; Niobium compounds; System-on-a-chip; Titanium compounds;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979651
