High-level Design Environments for FPGA-based Content Processing

Content processing of network packets requires real-time rates and high throughput, which a platform field programmable gate array (FPGA) can provide. It also requires a high-level design approach that allows time-to-market deadlines to be met. The paper introduces a two-step development process that allows the enhanced memory and I/O facilities of a content processor to be utilized but also avail of the more complete simulation and debug facilities on a compatible development board. This can be achieved by providing a complimentary or shadow design environment. High-level design is available for FPGAs in terms of hardware compilation and the provision of an on-chip runtime environment (RTE). The Tarari content processor supports both of these but investigation has shown that the RC200 development board assists in reducing design turn-around time.