Title :
Process variability-induced timing failures— A challenge in nanometer CMOS low-power design
Author :
Zhang, Xiaonan ; Bai, Xiaoliang
Author_Institution :
Qualcomm Inc., San Diego, CA
Abstract :
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage (DOS) chart. We propose a circuit design optimization and verification methodology that considers process variability.
Keywords :
CMOS digital integrated circuits; delay circuits; low-power electronics; network synthesis; timing; circuit design optimization; delay overlapping stage chart; digital timing; intradie random variability; low-power digital circuit designs; nanometer CMOS low-power design; process variability-induced timing failures; verification methodology; CMOS process; CMOS technology; Circuit synthesis; Delay; Digital circuits; Inverters; Robustness; Semiconductor device modeling; Threshold voltage; Timing;
Conference_Titel :
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-1810-7
Electronic_ISBN :
978-1-4244-1811-4
DOI :
10.1109/ICICDT.2008.4567269
