Title :
Noise verification across 3 levels of packaging hierarchy for the IBM G5/G6 mainframes
Author :
Smith, H. ; Kuppinger, S. ; Venkatachalam, P. ; Becker, W.
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
This paper describes the noise verification process across three levels of packaging for the IBM S/390 G5/G6 system. With over 11,000 critical nets in the system the design philosophy is founded on checking of noise magnitude on every net within the Central Electronics Complex (CEC). The CEC includes an MCM, the board, and memory cards. Description of the noise checking methodology as well as identifying nets exceeding the receiver noise immunity, the electrical characterization, geometrical extraction, transmission line effects, Delta-I calculations and statistical noise summation results will be presented
Keywords :
IBM computers; mainframes; noise; packaging; Central Electronics Complex; Delta-I noise; IBM S/390 G5/G6 mainframe; MCM; electrical characteristics; geometrical extraction; memory card; noise verification; packaging; receiver noise immunity; statistical noise summation; transmission line effects; Active noise reduction; Circuit noise; Electromagnetic coupling; Electromagnetic interference; Integrated circuit interconnections; Laboratories; Noise level; Packaging; Power transmission lines; Wiring;
Conference_Titel :
Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-5908-9
DOI :
10.1109/ECTC.2000.853244
