Accelerating Strategy for Functional Test of NoC Communication Fabric

Testing of network-on-chip (NoC) communication fabric draws more and more concern recently. Previous research show that the functional test of NoC can achieve nearly 100% structural fault coverage for the network switches, and the test approach based on functional test can be applied at full operation speed which original scan-based test approaches are hard to reach. The main novel contribution of this paper is an accelerating strategy for the NoC functional testing, including the “throughway” design of switches and its corresponding test configurations. The main concept is to organize the test configurations so that after boundary switches are proved to be fault-free, they could be reused as TAM of the other inner switches. Experimental results shows that comparing to some prior work, the proposed recursive test scheme using the accelerating strategy could reduce the complexity of test application time from O(N²) to O(N). The test scheme also has lower ambiguity of detected faults with same high fault-coverage. Experimental results show the proposed structure has low area cost and power consumption.