Dual-Vth based double-edge explicit-pulsed level-converting flip-flops

Clustered voltage scaling (CVS) systems is an efficient power reduction technique. One of the design challenges in CVS is the efficient level-converting flip-flop (LCFF) with less overhead in power and delay. In this paper, a level converting flip-flop based pass-transisor logic (LCFFBPT) and a static level converting flip-flop (SLCFF) are proposed, respectively. In addition, the two level-converting flip-flops can leverage availability of a second V_th to maintain good speed characteristics and less leakage power consumption. In the terms of the power delay product (PDP), based on simulation results using HSPICE in 45nm CMOS technology, the proposed flip-flops exhibit up to 68% reduction compared to existing level-converting flip-flops.