Title :
Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji
Abstract :
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce VT variations.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; integrated circuit design; large scale integration; nanoelectronics; MOSFET; SRAM cells; logic gates; low-voltage limitations; memory designer; nano-scale CMOS LSI; threshold voltage; CMOS logic circuits; Degradation; Flip-flops; Logic arrays; Logic circuits; MOSFETs; Random access memory; Read-write memory; Subthreshold current; Voltage;
Conference_Titel :
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-1810-7
Electronic_ISBN :
978-1-4244-1811-4
DOI :
10.1109/ICICDT.2008.4567273
