Title :
Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure
Author :
Pai, Chih-Yun ; Li, Katherine Shu-Min
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sun Univ., Kaohsiung, Taiwan
Abstract :
This paper proposes a resilient scheme to achieve maximal interconnect fault tolerance, reliability and yield for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this scheme can tolerate faulty connections by efficiently finding alternative paths with modified Longest Common Subsequence. This scheme is compatible with previous interconnect detection and diagnosis methods, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple faults. Furthermore, this scheme can identify connections which will cause communication failure if they are faulty. With this knowledge, designers can significantly improve interconnect reliability by augmenting such vulnerable connections. Experimental results show that alternative paths can be found for almost all paths in this scheme, this it provides a way to achieve fault-tolerant and reliability/yield improvement.
Keywords :
fault tolerant computing; integrated circuit interconnections; integrated circuit reliability; integrated circuit yield; interconnect fault tolerance; interconnect reliability; interconnect structure; maximal resilience; yield enhancement; Fault tolerance; Fault tolerant systems; Integrated circuit interconnections; Maintenance engineering; Oscillators; Resilience; System-on-a-chip; fault-tolerant routing; interconnect detection; interconnect diagnosis; interconnect resilience; oscillation ring;
Conference_Titel :
Test Symposium (ATS), 2010 19th IEEE Asian
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-8841-4
DOI :
10.1109/ATS.2010.53