Title :
Improvement of 48 nm TANOS NAND Cell Performance by Introduction of a Removable Encapsulation Liner
Author :
Beug, M.F. ; Melde, T. ; Paul, J. ; Bewersdorff-Sarlette, U. ; Czernohorsky, M. ; Beyer, V. ; Hoffmann, R. ; Seidel, K. ; Löhr, D.A. ; Bach, L. ; Knoefler, R. ; Tilke, A.T.
Author_Institution :
Qimonda Dresden GmbH & Co. OHG, Dresden
Abstract :
This paper presents charge trapping (CT) cells integrated with a sacrificial liner at the word line (WL) side wall which improves significantly the erase and retention characteristics, currently the main issues in CT memory devices.
Keywords :
NAND circuits; storage management chips; CT memory devices; TANOS NAND cell; charge trapping cells; encapsulation liner; size 48 nm; word line; Aluminum oxide; Breakdown voltage; Electrodes; Encapsulation; Etching; High K dielectric materials; High-K gate dielectrics; Nonvolatile memory; Pulse measurements; Silicon compounds;
Conference_Titel :
Memory Workshop, 2009. IMW '09. IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-3762-7
DOI :
10.1109/IMW.2009.5090595
