Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory

Author

Van den Bosch, G. ; Breuil, L. ; Cacciato, A. ; Rothschild, A. ; Jurczak, M. ; Van Houdt, J.

Author_Institution

IMEC, Leuven

fYear

2009

fDate

10-14 May 2009

Firstpage

1

Lastpage

2

Abstract

TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V,h program/erase window monotonically shifts upward whereas the V_fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process.

Keywords

NAND circuits; aluminium compounds; energy gap; flash memories; integrated memory circuits; interface states; silicon compounds; Si band gap; SiO₂-Si₃N₄-Al₂O₃; TANOS NAND flash memory; TANOS endurance; blocking dielectric; charge compensation; donor trap formation; electrical stress; interface traps; memory stack process; program-erase cycling; substrate-tunnel oxide interface; tunnel oxide; window instability; Capacitors; Channel bank filters; Charge carrier processes; Charge pumps; Monitoring; Nonvolatile memory; Photonic band gap; Stress; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop, 2009. IMW '09. IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4244-3762-7

Type

conf

DOI

10.1109/IMW.2009.5090596

Filename

5090596