Thermal Safe High Level Test Synthesis for Hierarchical Testability

High temperature in test process may invalidate a test due to extra delay, or even damage the circuit under test. Therefore, a thermal-safe test can avoid undesirable yield loss due to the extra delay induced by high temperature. Traditional high level test synthesis approaches just improve hierarchical testability of circuits and minimize test application time. If the thermal effects are ignored, the higher test power density may produce unacceptable high temperature even though thermal management is carried out in the functional mode. Since the thermal-aware design cannot achieve thermal-safe hierarchical testing, a thermal-safe high level test synthesis approach is proposed in this paper to deal with this problem. In the proposed test synthesis procedure, the given temperature constraints will be satisfied in the test environment construction process. Experimental results show that the proposed test synthesis method can provide thermal-safe hierarchical test and shorten test application time compared to conventional high-level test synthesis approaches.