Performance models for optimizing a hierarchical-bus multiprocessor architecture

In order to build high-performance multiprocessor systems that take advantage of current VLSI technologies, a new architecture, called Hierarchical-Bus Multiprocessor Architecture, has been proposed. This paper develops analytical models for the performance analysis of its communication network. The performance index used for comparisons is the mean response time of the communication network. To keep the analysis tractable, some simplifying assumptions were made. Due to the size of the complete queueing network model, an approximate model was developed. Validation of the analytical model against a simulation study reveals that this model predicts performance of the communication network architecture with adequate accuracy