Title :
3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics
Author :
Ernst, T. ; Bernard, E. ; Dupre, C. ; Hubert, A. ; Becu, S. ; Guillaumot, B. ; Rozeau, O. ; Thomas, O. ; Coronel, P. ; Hartmann, J.-M. ; Vizioz, C. ; Vulliet, N. ; Faynot, O. ; Skotnicki, T. ; Deleonibus, S.
Author_Institution :
CEA-LETI, Minatec, Grenoble
Abstract :
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.
Keywords :
CMOS integrated circuits; integrated circuit design; nanoelectronics; nanowires; 3D multichannels; independent gate operation; multichannel CMOS architectures; nanoelectronics; non planar CMOS devices; stacked nanowires technologies; CMOS technology; Epitaxial growth; Etching; FinFETs; Nanoelectronics; Nanowires; Robustness; Silicon; Tin; Transistors; CMOS; CMOS scaling; FinFET; Multichannel; PhiFET;
Conference_Titel :
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-1810-7
Electronic_ISBN :
978-1-4244-1811-4
DOI :
10.1109/ICICDT.2008.4567292
