Title :
On Bias in Transition Coverage of Test Sets for Path Delay Faults
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
A test for a delay fault can be considered as covering a transition on one or more lines. A bias in the transition coverage of a delay test set implies that more rising or more falling transitions are covered by the test set. Such a bias is not captured by fault coverage metrics that consider both types of transitions together. We study the bias in the transition coverage of test sets for path delay faults. The results demonstrate that the bias is circuit-dependent. It also depends on the type of two-pattern tests used. In general, broadside tests show more bias than skewed-load tests, while enhanced-scan tests show little bias. We also consider the use of partial-enhanced-scan for reducing the bias exhibited by broadside tests.
Keywords :
delay circuits; design for testability; partial-enhanced-scan; path delay faults; test sets; transition coverage; Circuit faults; Delay; Design automation; Discrete Fourier transforms; Fault detection; Integrated circuit modeling; broadside tests; path delay faults; scan circuits; skewed-load tests; transition coverage;
Conference_Titel :
Test Symposium (ATS), 2010 19th IEEE Asian
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-8841-4
DOI :
10.1109/ATS.2010.66