DocumentCode :
2170279
Title :
[Title page]
fYear :
2009
fDate :
20-24 April 2009
Abstract :
The following topics were dealt with: interconnection technology; multicore system-on-chip; reconfigurable hardware; MPSoC; task allocation; reliability; scheduling; timing analysis; embedded real-time systems; system-level synthesis; optimization; high-level modeling; verification; system-level test; system-level debug; model-based design; hardware-software system integration; network on chip; analogue layout synthesis; aerospace systems; MEMS; mixed-signal applications;variability test; circuit marginality; flash memory management; space exploration; power optimization techniques; open source hardware IP; nanoelectronics; embedded systems security; on-line testing; fault tolerance;vertical integration; disaggregation; CNTFET; cryptographic functions; runtime checking; contactless testing; multiprocessor real-time systems; analogue synthesis; nonvolatile memory technology; ESL methodology; on-chip communication; on-line error detection; software support; sizing; placement; planning; packaging; automotive systems; programmable SoCs; advanced low-power memory; thermal management; multicore platforms; debugging; diagnosis; health-care electronics; industrial system designs; multimedia; NoC performance optimization; automotive networks,; sensors; architectural synthesis; test pattern generation; interconnect models; industrial system design flow; mass market applications; multicore products; computation models; forward error correction; signal processing; design-for-test; memory-aware compiler techniques; mixed-signal technology design; mixed technology design; high-level power management; media processing; logic synthesis; decomposition techniques; restructuring techniques; test data compression; automation; model generation; model implementation; field programmable architectures; digital design; advanced SAT techniques; baseband processors; MIMO communication systems; UWB communication systems; system level simulation; system level validation; RF testing; DFX engine- ring; multicycle design.
Keywords :
MIMO communication; aerospace engineering; analogue integrated circuits; automation; automotive electronics; cryptography; data compression; design for testability; embedded systems; error correction; error detection; fault tolerance; flash memories; formal verification; hardware-software codesign; health care; integrated circuit interconnections; logic devices; low-power electronics; micromechanical devices; mixed analogue-digital integrated circuits; multimedia systems; multiprocessing systems; nanoelectronics; network-on-chip; optimisation; packaging; program debugging; programmable circuits; random-access storage; reconfigurable architectures; reliability; scheduling; sensors; signal processing; simulation; system-on-chip; task analysis; thermal management (packaging); thin film devices; timing; ultra wideband communication; CNTFET; DFX engineering; ESL methodology; MEMS; MIMO communication systems; MPSoC; NoC performance optimization; RF testing; UWB communication systems; advanced SAT techniques; advanced low-power memory; aerospace systems; analogue layout synthesis; architectural synthesis; automation; automotive networks; automotive systems; baseband processors; circuit marginality; computation models; contactless testing; cryptographic functions; debugging; decomposition techniques; design-for-test; diagnosis; digital design; disaggregation; embedded real-time systems; embedded systems security; fault tolerance; field programmable architectures; flash memory management; forward error correction; hardware-software system integration; health-care electronics; high-level modeling; high-level power management; industrial system design flow; industrial system designs; interconnect models; interconnection technology; logic synthesis; mass market applications; media processing; memory-aware compiler techniques; mixed technology design; mixed-signal applications; mixed-signal technology design; model generation; model implementation; model-based design; multicore platforms; multicore products; multicore system-on-chip; multicycle design; multimedia; multiprocessor real-time systems; nanoelectronics; network on chip; nonvolatile memory technology; on-chip communication; on-line error detection; on-line testing; open source hardware IP; packaging; placement; planning; power optimization techniques; programmable SoCs; reconfigurable hardware; reliability; restructuring techniques; runtime checking; scheduling; sensors; signal processing; sizing; software support; space exploration; system level simulation; system level validation; system-level debug; system-level synthesis; system-level test; task allocation; test data compression; test pattern generation; thermal management; timing analysis; variability test; verification; vertical integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090611
Filename :
5090611
Link To Document :
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