Title :
Logic synthesis for efficient pseudoexhaustive testability
Author :
Krasniewski, Andrzej
Author_Institution :
University of Rochester
Keywords :
Boolean functions; Circuit synthesis; Circuit testing; Combinational circuits; Design methodology; Input variables; Logic design; Logic testing; Signal synthesis; Test pattern generators;
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
