DocumentCode
2170330
Title
Logic synthesis for efficient pseudoexhaustive testability
Author
Krasniewski, Andrzej
Author_Institution
University of Rochester
fYear
1991
fDate
21-21 June 1991
Firstpage
66
Lastpage
72
Keywords
Boolean functions; Circuit synthesis; Circuit testing; Combinational circuits; Design methodology; Input variables; Logic design; Logic testing; Signal synthesis; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location
IEEE
Print_ISBN
0-89791-395-7
Type
conf
Filename
979691
Link To Document