Title :
Correlation-reduced scan-path design to improve delay fault coverage
Author :
Mao, Weiwei ; Ciletti, Michael D.
Author_Institution :
University of Colorado
Keywords :
Algorithm design and analysis; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Hardware; Latches; Permission; Sequential analysis;
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
