Software-Based Self-Testing of Processors Using Expanded Instructions

In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based self-testing (SBST) of processors. First, mappings between expanded instructions and signals are obtained through data mining, and they are used to impose value ranges of expanded instructions on component signals and generate instruction-level constraints. Second, virtual circuits are established based on the instruction-level constraints, and test patterns are generated for the constrained components. Third, test patterns are translated into test instructions according to the values of controlling signals and constraints for their mappings to instructions, and an SBST program is produced after assembling the test instructions. Experimental results on the Parwan processor show that the proposed ATIG technique can achieve 94.8% stuck-at fault coverage, which is close to that of the full scan test generation method. In addition, it can cut down 57% test volume of the previous random pattern generation based SBST technique, while the test time reduces to one thirteenth of the previous SBST technique.