Title :
A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends
Author :
Mohajerin, Mani ; Chen, Chunhong ; Abdel-Raheem, Esam
Author_Institution :
Dept. of Electr. & Comput. Eng., Windsor Univ., Ont., Canada
Abstract :
A 12-bit, 40 MS/s pipelined analog-to-digital converter (ADC) is designed in 0.18-μm CMOS technology with 1.8 V single power supply. The proposed ADC architecture uses a combination of current-mode and voltage-mode stages to, significantly, reduce both power dissipation and area compared to conventional fully differential voltage-mode pipeline ADCs. Simulation results are provided and indicate that the proposed ADC has potential to be deployed in the video analog front-ends.
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; power supply circuits; 0.18 mum; 1.8 V; CMOS technology; current-mode; pipeline ADC; pipelined analog-to-digital converter; video analog front ends; voltage-mode stages; Analog-digital conversion; CMOS technology; Error correction; Mirrors; Operational amplifiers; Pipelines; Power dissipation; Power supplies; Switched capacitor circuits; Voltage;
Conference_Titel :
Communications, Computers and signal Processing, 2005. PACRIM. 2005 IEEE Pacific Rim Conference on
Print_ISBN :
0-7803-9195-0
DOI :
10.1109/PACRIM.2005.1517360
