DocumentCode
2170509
Title
Design and optimization of multi-tap DFE for high-speed backplane data communications
Author
Li, Miao ; Wang, Shoujun ; Chen, Jing ; Kwasniewski, Tad
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear
2005
fDate
24-26 Aug. 2005
Firstpage
601
Lastpage
604
Abstract
Multi-tap decision-feedback-equalization (DFE) is proposed to counteract inter-symbol interference (ISI) in high-speed backplane data communications. A MATLAB program has been developed to optimize the DFE tap coefficients for a given backplane channel. A multi-tap DFE receiver with an optional analog pre-equalizer implemented in 0.18 μm CMOS technology demonstrates 8 Gb/s operation with PRBS15 data over a 34" FR4 backplane.
Keywords
CMOS analogue integrated circuits; data communication; decision feedback equalisers; interference suppression; intersymbol interference; 0.18 mum; 8 Gbit/s; CMOS technology; ISI; analog pre-equalizer; decision-feedback-equalization; high-speed backplane data communications; intersymbol interference; multitap DFE; Backplanes; CMOS technology; Clocks; Data communication; Decision feedback equalizers; Delay effects; Design optimization; Finite impulse response filter; Intersymbol interference; MATLAB;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and signal Processing, 2005. PACRIM. 2005 IEEE Pacific Rim Conference on
Print_ISBN
0-7803-9195-0
Type
conf
DOI
10.1109/PACRIM.2005.1517361
Filename
1517361
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