Design of low-power quaternary flip-flop based on dynamic source-coupled logic

Author

Haixia, Wu ; Shunan, Zhong ; Zhentao, Sun ; Xiaonan, Qu ; Yueyang, Chen

Author_Institution

Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

826

Lastpage

828

Abstract

A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18μm CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.

Keywords

CMOS integrated circuits; VLSI; flip-flops; integrated circuit design; logic design; low-power electronics; multivalued logic; CMOS technology; HSPICE simulation; VLSI system; differential-pair circuit; dynamic source-coupled logic; low-power quaternary flip-flop; multiple-valued source-coupled logic; size 0.18 mum; threshold detectors; CMOS integrated circuits; Detectors; Generators; Inverters; Latches; Power dissipation; Very large scale integration; Multiple-value Logic; Quaternary Flip-Flop; Source-coupled Logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Ningbo

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6066389

Filename

6066389