The design and verification of packet processing engine model using SystemC

Author

Ma, Pei-Jun ; Zhao, Qing-He ; Fan, Yong ; Liu, Meng ; Li, Kang

Author_Institution

Dept. Microelectron., Xidian Univ., Xi´´an, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

1099

Lastpage

1101

Abstract

The traditional hardware description languages (VHDL and Verilog) is not suitable for system-level modeling and Hardware Software Codesign, while the SystemC language is more suitable than the traditional HDL language for system-level modeling. This paper describes the packet processing engine(PPE) characteristics of XDNP network processor, analyze the advantage of system-level modeling in SystemC language, and use the SystemC language for the system-level modeling of the packet processing engine. In addition an independent simulation model is built, and the performance of packet processing engine is analyzed and verificated. Compared with the traditional hardware description language model we can obtain about 1.5 times simulation speed as much as that of HDL model.

Keywords

C language; formal verification; hardware description languages; hardware-software codesign; logic design; HDL language; PPE characteristics; SystemC language; VHDL; Verilog; XDNP network processor; hardware description languages; hardware software codesign; independent simulation model; packet processing engine characteristics; packet processing engine model; system-level modeling; Analytical models; Engines; Hardware; Instruction sets; Object oriented modeling; Registers; System-on-a-chip; Packet Processing Engine; SoC; SystemC;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Ningbo

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6066395

Filename

6066395