Frequency domain compensation of spurious sidebands in A/D circuits

In a non-ideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used as a clock signal, it creates spurious tones in the sampled data. Our prior work used a training signal to estimate the distortions and then correct the samples. In this work, we propose an alternative approach that estimates and removes the distortions directly from the sampled data without a training signal. Simulations indicate that the proposed solution is able to reduce the root-mean-square (RMS) sampling errors to about 15% of the original values.