Title :
Two-channel time-interleaved pipelined ADC using shared amplifiers
Author :
Zhuo, Zhang ; Shun, Zhong ; Xing-hua, Wang
Author_Institution :
Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China
Abstract :
A pipelined ADC using shared amplifiers in two-channel time-interleaved design is proposed. The two channels have a unify sample and hold amplifier. In the time-interleaved pipelined part, the large mismatch between the channels is reduced by the shared amplifier in the same stage. And power consumption and chip area also been decreased. Under SMIC 0.35um 1P6M CMOS process with 3.3V supply, the SNR is higher than 60dB with the condition that the sampling rate is 200MHz and the input frequency is scanned from 1MHz to 80MHz. The typical current consumption is about 40mA.
Keywords :
CMOS digital integrated circuits; amplifiers; analogue-digital conversion; low-power electronics; sample and hold circuits; SMIC 1P6M CMOS process; chip area; current consumption; frequency 1 MHz to 80 MHz; pipelined ADC; power consumption; sample and hold amplifier; sampling rate; shared amplifier; size 0.35 mum; two-channel time-interleaved design; voltage 3.3 V; Analog-digital conversion; CMOS process; Circuits; Delay; Design optimization; Energy consumption; Frequency; Power dissipation; Sampling methods; Testing; CMOS; amplifier shared; piepelined; time-interleaved;
Conference_Titel :
Computer and Automation Engineering (ICCAE), 2010 The 2nd International Conference on
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-5585-0
Electronic_ISBN :
978-1-4244-5586-7
DOI :
10.1109/ICCAE.2010.5452031
