DocumentCode
2171028
Title
Scaling OLTP applications on commodity multi-core platforms
Author
Cui, Yan ; Chen, Yu ; Shi, Yuanchun
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear
2010
fDate
28-30 March 2010
Firstpage
134
Lastpage
143
Abstract
Multi-core processor architectures can have significant performance advantage over traditional single core designs, which are limited by power and processor complexity. Predictions based on Moore´s Law state that a processor chip may accommodate thousands of cores in 5-10 years. Can software scale with the number of cores and achieve the performance potential? This paper uses two OLTP (online transaction processing) applications (TPCC-UVa and Sysbench-OLTP) as a case study to investigate this question and determine what the performance bottlenecks are. On an Intel 8-core platform, these applications (with slight modifications to run well on a many-core platform) achieve a speedup (in terms of the transaction throughput) of 3.68 and 5.26, respectively. To find the scalability bottlenecks the paper proposes a method based on function´s scalability value metric. Functions with a high scalability value limit the scalability. By looking at the functions with the highest scalability value across all functions in the kernel, libraries, and application processes, the paper finds that database buffer pool contention, database synchronization primitives, scheduler overhead and lock contention in System V IPC are the main bottlenecks for TPCC-UVa. In Sysbench-OLTP, database synchronization primitives and the kernel scheduler limit scalability. The paper also explores several ideas such as scalable database lock, scalable spin lock and RCU-based IDR API to improve the scalability.
Keywords
data mining; microprocessor chips; multiprocessing systems; Moore law; RCU-based IDR API; commodity multicore platforms; database synchronization; kernel scheduler; multicore processor architectures; online transaction processing; processor chip; processor complexity; single core designs; sysbench-OLTP; Application software; Computer architecture; Databases; Kernel; Libraries; Moore´s Law; Multicore processing; Scalability; Software performance; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance Analysis of Systems & Software (ISPASS), 2010 IEEE International Symposium on
Conference_Location
White Plains, NY
Print_ISBN
978-1-4244-6023-6
Electronic_ISBN
978-1-4244-6024-3
Type
conf
DOI
10.1109/ISPASS.2010.5452034
Filename
5452034
Link To Document