Silicon and III-V nanoelectronics

Sustaining Moore´s Law of doubling CMOS transistor density every twenty four months will require not only shrinking the transistor dimensions, but also introduction of new materials and new device architectures. We discuss in this talk the recent innovations that are being researched and pursued to enable high performance Si-based CMOS nanoelectronics such as the use of highly strained Si channel for enhanced carrier transport, high-K dielectric and metal gate stack for low gate leakage, and non-planar multiple gate transistors for reduced short channel effects. In the future, further power-performance benefit may even potentially be achieved by incorporating III-V compound semiconductor nanoelectronics as ultra-high channel mobility materials. Some novel benchmarking results comparing III-V transistors to state-of-the-art advanced Si transistors will be presented.