Title :
A low power and compact desktop ATM PMD
Author :
Wakayama, Y. ; Nakano, F. ; Takeuchi, J. ; Honda, N. ; Ishii, K. ; Sakamoto, T. ; Fujii, T.
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 μm CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm2 are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized
Keywords :
CMOS digital integrated circuits; asynchronous transfer mode; 0.35 micron; 25.6 Mbit/s; 74 mW; CMOS process; PMD sublayer circuit; UTP cable equalizer circuit; clock recovery circuit; desktop ATM interface; die area; low power six port chip; CMOS process; Cable shielding; Circuits; Clocks; Dynamic range; Energy consumption; Equalizers; Large scale integration; MOSFETs; Resistors;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606641
