Title :
Timing- and constraint-oriented placement for interconnected LSIs in mainframe design
Author :
Ogawa, Yasushi ; Itoh, Tsutomu ; Miki, Yoshio ; Ishii, Tatsuki ; Sato, Yasuo ; Toyoshima, Reiji
Author_Institution :
Kanagawa Works, Hitachi, Ltd.
Keywords :
Delay; Design automation; Error correction; Laboratories; Large scale integration; Logic; Permission; Physics computing; Search methods; Timing;
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
