• DocumentCode
    2171243
  • Title

    Timing- and constraint-oriented placement for interconnected LSIs in mainframe design

  • Author

    Ogawa, Yasushi ; Itoh, Tsutomu ; Miki, Yoshio ; Ishii, Tatsuki ; Sato, Yasuo ; Toyoshima, Reiji

  • Author_Institution
    Kanagawa Works, Hitachi, Ltd.
  • fYear
    1991
  • fDate
    21-21 June 1991
  • Firstpage
    253
  • Lastpage
    258
  • Keywords
    Delay; Design automation; Error correction; Laboratories; Large scale integration; Logic; Permission; Physics computing; Search methods; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1991. 28th ACM/IEEE
  • Conference_Location
    IEEE
  • Print_ISBN
    0-89791-395-7
  • Type

    conf

  • Filename
    979724
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2171243