Incorporating Instruction-Based Sampling into AMD CodeAnalyst

Author

Drongowski, Paul ; Yu, Lei ; Swehosky, Frank ; Suthikulpanit, Suravee ; Richter, Robert

fYear

2010

fDate

28-30 March 2010

Firstpage

119

Lastpage

120

Abstract

Instruction-Based Sampling (IBS) is a hardware mechanism that improves the accuracy of profiles. IBS is supported by AMD Family 10h processors. The processing pipeline of an AMD Family 10h processor is separated into two loosely coupled phases: A front-end phase that fetches AMD64 instruction bytes and a back-end phase that execute "ops" which issue from decoded AMD64 instructions. An op is an internal, fixed-width instruction which is executed by the pipeline stages in the execution phase. More than one op may issue from an instruction. Due to the decoupling, IBS samples fetches and ops separately, i.e., there are two independent sampling mechanisms. We will concentrate on IBS op sampling in this discussion.

Keywords

instruction sets; microprocessor chips; pipeline processing; AMD CodeAnalyst; AMD family processor; fixed-width instruction; independent sampling mechanisms; instruction-based sampling; pipeline processing; Application software; Counting circuits; Delay; Hardware; Microarchitecture; Performance analysis; Personal communication networks; Pipelines; Sampling methods; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Performance Analysis of Systems & Software (ISPASS), 2010 IEEE International Symposium on

Conference_Location

White Plains, NY

Print_ISBN

978-1-4244-6023-6

Electronic_ISBN

978-1-4244-6024-3

Type

conf

DOI

10.1109/ISPASS.2010.5452049

Filename

5452049