DocumentCode :
2171657
Title :
A synthesis-based test generation and compaction algorithm for multifaults
Author :
Devadas, Srinivas ; Keutzer, Kurt ; Malik, Sharad
Author_Institution :
Princeton University
fYear :
1991
fDate :
21-21 June 1991
Firstpage :
359
Lastpage :
365
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Compaction; Delay; Fabrication; Integrated circuit testing; Network synthesis; Permission; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
Type :
conf
Filename :
979742
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2171657
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