Title :
Highly Reliable Interface of Self-aligned CuSiN process with Low-k Sic barrier dielectric (k3.5) for 65nm node and beyond
Author :
Usami, T. ; Ide, T. ; Kakuhara, Y. ; Ajima, Y. ; Ueno, K. ; Maruyama, T. ; Yu, Y. ; Apen, E. ; Chattopadhyay, K. ; van Schravendijk, B. ; Oda, N. ; Sekine, M.
Author_Institution :
Process Technol. Div., NEC Electron. Corp., Sagamihara
Abstract :
A highly reliable interface using a self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) has been developed for 65nm node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure. In addition, 39times via electro-migration (EM) improvement and 1.5times better TZDB were obtained in comparison to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TEM-EELS. According to these analyses, the mechanism for performance enhancement is proposed
Keywords :
X-ray photoelectron spectra; copper compounds; electromigration; electron energy loss spectra; low-k dielectric thin films; silicon compounds; transmission electron microscopy; 65 nm; CuSiN; EM improvement; NH3 plasma pretreatment process; SiC; TEM-EELS; XPS; electromigration improvement; low-k barrier dielectrics; self-aligned process; Capacitance; Copper; Dielectrics; Optical microscopy; Plasmas; Silicon carbide; Silicon compounds; Surface morphology; Surface resistance; Testing;
Conference_Titel :
Interconnect Technology Conference, 2006 International
Conference_Location :
Burlingame, CA
Print_ISBN :
1-4244-0104-6
DOI :
10.1109/IITC.2006.1648665
